Novel structure to reduce the degradation of the Q value of an inductor caused by via resistance

ABSTRACT

A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias. The invention can further be extended by creating at least one second via through the thick layer of polyimide aligned with at least one of the created first vias. A patterned and etched layer of metal that fills the second via creates a re-distribution layer on the surface of the thick layer of polyimide for flip chip interconnects.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention relates to the fabrication of integrated circuitdevices, and more particularly, to a method and structure of creating aninductor as part of a semiconductor device in such a manner that anegative impact of via resistance is sharply reduced.

[0003] (2) Description of the Prior Art

[0004] Integrated Circuits (IC's) are typically formed in or on thesurface of a semiconductor substrate, electrical circuit elements of theindividual IC's are connected internally to the semiconductor surface onwhich the IC's are formed. IC's that are formed in or on the surface ofa substrate are mostly active digital processing devices but can alsoinclude analog processing devices. In addition, discrete passivecomponents can be formed that function with active semiconductor devicesand that are preferably created using semiconductor device technologyprocedures and equipment.

[0005] One of the major challenges in the creation of analog processingcircuitry using digital processing procedures and equipment is that anumber of components used for analog circuitry are large in size and aretherefore not easy to integrate into devices that typically have featuresizes approaching the sub-micron range. The main components that offer achallenge in this respect are capacitors and inductors, both thesecomponents are, for typical analog processing circuitry, of considerablesize.

[0006] A typical application of an inductor is in the field of modernmobile communication that makes use of compact high-frequency equipment.Continued improvements in the performance of such equipment placecontinued emphasis on lowering the power consumption of the equipment,on reducing the size of the equipment, on increasing the frequency ofthe applications and on creating low noise levels.

[0007] Typically, inductors that are created on the surface of asubstrate are of a spiral shape whereby the spiral is created in a planethat is parallel with the plane of the surface of the substrate.Conventional methods that are used to create the inductor on the surfaceof a substrate suffer several limitations. Most high Q inductors formpart of a hybrid device configuration or of Monolithic MicrowaveIntegrated Circuits (MMIC's) or are created as discrete components, thecreation of which is not readily integratable into a typical process ofIntegrated Circuit manufacturing.

[0008] The parameter by which the applicability of an inductor istypically indicated is the Quality (Q) factor of the inductor. Thequality factor Q of an inductor is defined as Q=Es/El=F₀L/R wherein Esis the energy that is stored in the reactive portion of the component,El is the energy that is lost in the reactive portion of the component,F₀ is the resonant frequency of oscillation of the resonant circuit ofwhich the inductor is a component, L is the inductance of the inductorand R is the resistance of the inductor. The higher the quality of thecomponent, the closer the resistive value of the component approacheszero while the Q factor of the component approaches infinity. Thequality factor Q is dimensionless. A Q value of greater than 100 isconsidered very high for discrete inductors that are mounted on thesurface of Printed Circuit Boards. For inductors that form part of anintegrated circuit, the Q value is typically in the range between about3 and 10.

[0009] In typical applications, the redistribution inductor, created ina plane that is parallel with the surface of the substrate over whichthe inductor is created, has very low serial resistance. However, theconventional via that is provided between the inductor and theunderlying metal contributes a finite value of resistance which forms abarrier in the effort to reduce the resistive value of the inductor andto thereby improve the Q value of the inductor. The invention addressesthis concern in the creation of a planar inductor.

[0010] U.S. Pat. No. 6,054,329 (Burghartz et al.) shows a spiralinductor.

[0011] U.S. Pat. No. 5,539,241, (Adidi et al.) and U.S. Pat. No.5,478,773 (Dow et al.) show related spiral inductors and via processes.

SUMMARY OF THE INVENTION

[0012] A principle objective of the invention is to reduce the resistivecomponent of a spiral inductor.

[0013] A new method and structure is provided to connect a planar,spiral inductor to underlying interconnect metal, the patternedinterconnect metal has been created over a semiconductor surface. Alayer of dielectric followed by a layer of passivation is deposited overthe semiconductor surface, including the surface of the underlyinginterconnect metal. Large first vias are created through the layers ofpassivation and dielectric. The large first vias align with thepatterned interconnect metal, providing low-resistivity points ofinterconnect between the spiral inductor, which is created on thesurface of the layer of passivation concurrent with the creation of thelarge first vias, and the patterned interconnect metal. A thick layer ofpolyimide is deposited over the surface of the layer of passivation,including the surface of the spiral inductor and the large first vias.The invention can further be extended by creating at least one secondvia through the thick layer of polyimide aligned with at least one ofthe created first vias. A patterned and etched layer of metal that fillsthe second via creates a re-distribution layer on the surface of thethick layer of polyimide for flip chip interconnects

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 shows a top view of a conventional spiral inductor.

[0015]FIG. 2 shows a cross section of the conventional spiral inductorof FIG. 1.

[0016]FIG. 3 shows the electrical equivalency circuit of a spiralinductor.

[0017]FIG. 4 shows the inductor of the invention, including the largefirst vias that have been used to connect the inductor to the underlyingpatterned interconnect metal.

[0018]FIG. 5 shows the inductor of the invention whereby a first viathat is used for the interconnect of the inductor is extended by asecond via to form a re-distribution layer for flip chip application.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Referring now specifically to FIG. 1, there is shown a top viewof a spiral inductor that has been created overlying the surface of asemiconductor substrate. All the lines that form the spiral inductorhave been highlighted in order to facilitate cross referencing with thecross section of this inductor that is shown in FIG. 2. The spiralinductor of FIG. 1 can be recognized as having two and a half loops, theinductor that is shown in top view in FIG. 1 is connected to surroundingcircuitry elements (not shown in FIG. 1) by means of the patternedinterconnect metal lines 14 and 16. The highlighted elements 15 and 17are two vias that provide the electrical connection between the(arbitrarily designated as) first line 18 of the inductor and theunderlying line 14, via 17 performs this function for the electricalinterconnection between the (arbitrarily designated as) last leg 28 ofthe inductor and the underlying line 16.

[0020] The current flow through the inductor can be identified asflowing from line 14 through via 15 through successively lines 18, 18′,20, 20′, 22, 22′, 24, 24′, 26, 26′, 28, the via 17 and out through theunderlying patterned line 16. The indicated direction of current flow isarbitrary and can be reversed from the sequence that has beenhighlighted.

[0021] The cross section that is shown in FIG. 2 (of the spiral inductorof FIG. 1) further highlights a number of the lines that have beenidentified under FIG. 1. Further highlighted in FIG. 2 are:

[0022]10, the surface of a semiconductor substrate on the surface ofwhich the spiral inductor is created

[0023]14 and 16, the patterned interconnect lines that connect theinductor to surrounding circuitry

[0024]30, a layer of dielectric that has been deposited over the surface10 of the semiconductor substrate including the surface of theinterconnect lines 14 and 16

[0025]32, a layer of passivation that has been deposited over thesurface of the layer 30 of dielectric.

[0026] All the other elements that have been highlighted in FIG. 2 havepreviously been discussed under FIG. 1 and do therefore not need to befurther discussed at this time.

[0027] It must be noted that conventional design uses a metal thicknessfor the layer of the spiral inductor, that is the height of the elements18, 20, 22, 24, 26 and 28, of about 2 μm. This observation will be usedas one of the means by which the resistive component of the inductorwill be reduced, this will be further discussed under FIGS. 3 and 4following. It must further be noted that vias 15 and 17 shown in crosssection in FIG. 2 are of conventional design, having a relatively smalldiameter in addition or having vertical sidewalls of the openings inwhich the vias are created.

[0028] The elements that are shown in FIG. 3 represent an equivalentcircuit diagram of the spiral inductor of FIGS. 1 and 2. The componentsthat make up this equivalent circuit can be described as follows:

[0029] Ls is the inductive value of the spiral inductor between the topsurface of vias 15 and 17, FIGS. 1 and 2

[0030] Rs is the resistive value of the spiral inductor between the topsurface of vias 15 and 17, FIGS. 1 and 2

[0031] Cs is the parasitic capacitance of the spiral inductor betweenthe top surface of vias 15 and 17, FIGS. 1 and 2

[0032] Cox1 is the cumulative parasitic capacitance between the topsurface of via 15 and the surface of the substrate 10, incurred in thelayer 32 of passivation, the layer 30 of dielectric and the interconnectmetal line 14

[0033] Cox2 is the cumulative parasitic capacitance between the topsurface of via 17 and the surface of the substrate 10, incurred in thelayer 32 of passivation, the layer 30 of dielectric and the interconnectmetal line 16

[0034] Csub1 is the cumulative parasitic capacitance between the lowerterminal of Cox1 on the surface of substrate 10 and circuit ground (notshown in FIG. 1 and 2)

[0035] Csub2 is the cumulative parasitic capacitance between the lowerterminal of Cox2 on the surface of substrate 10 and circuit ground (notshown in FIG. 1 and 2)

[0036] Rsub1 is the cumulative resistance between the lower terminal ofCox1 on the surface of substrate 10 and circuit ground (not shown inFIG. 1 and 2)

[0037] Rsub2 is the cumulative resistance between the lower terminal ofCox2 on the surface of substrate 10 and circuit ground (not shown inFIG. 1 and 2).

[0038] For the equivalent circuit configuration that is shown in FIG. 3,the following relation is valid:

[0039] Total Rs=Rs-metal+Rc-via, where Rs-metal is the series resistanceof the coils of the inductor between vias 15 and 17 on the surface ofthe layer 32 of passivation and Rc-via is the series resistance of thevias 15 and 17

[0040] This value of Total Rs is the total resistive component of thespiral inductor that has previously been highlighted, it is clear thatthe lines (or windings) of the inductor plus the resistance of the viacontribute to this total resistivity, this in accordance with therelation as shown.

[0041] Empirical experiments have shown that, after the thickness of themetal that is used to create the spiral inductor, that is the height ofthe lines that form the inductor as measured in a direction that isperpendicular to the surface of the underlying substrate 10, isincreased from a typical (prior art) value of 2 μm to between about 6and 26 μm, the following relationship becomes valid: TotalRs=(Rs-metal)/13+Rc-via. The factor 13 is derived from the fact that 26(the new height) divided by 2 (the prior art height) yields the value13. It is clear from this equation that the resistive component of themetal of the inductor has been significantly decreased as a contributingfactor to the Total Rs which results in the component Rc-via becomingthe dominant factor in determining the value for Total Rs. It thereforestands to reason that, if this contributing component of Rc-via isreduced, the value for Total Rs is further reduced. By therefore using alarge via, the value of Rc-via will approach zero and the value of Rsapproaches (Rs-metal)/13

[0042] The method of the invention to accomplish this is shown in crosssection in FIG. 4. The new elements that are highlighted in FIG. 4 arethe following:

[0043] vias 36 and 38, which take the place of the conventional vias 15and 17 of FIG. 2

[0044] metal lines 40, 42, 44 and 46 which take the place ofconventional metal lines 22, 24, 26 and 30 respectively

[0045]34, a thick layer of polyimide that has been deposited over thesurface of the layer 32 of passivation, including the surface of thespiral inductor.

[0046] It must be noted from the cross section that is shown in FIG. 4that:

[0047] the height of the lines 40, 44, 42 and 46 has been increased from(prior art value of) 2 μm to between about 6 and 26 μm

[0048] the preferred material for the metal lines 40, 44, 42 and 46 ofthe spiral inductor is gold or copper of platinum, to be deposited usingmethods of metal plating or screen printing

[0049] the height of the borders of vias 36 and 38 (those portions ofthe vias that overlay the surface of layer 32 of passivation) also hasbeen increased from (prior art value of) 2 μm to between about 6 and 26μm

[0050] vias 36 and 38 are significantly more robust than the (prior art)vias 15 and 17 of FIG. 2, thereby reducing the contributing resistivecomponent of these interconnect vias; the top surface of vias 36 and 38of the invention have typical dimensions of about 7×7 μm, this asopposed to conventional values that are typically used for lower levelsof metal of 0.17×0.17 μm

[0051] layer 34 of polyimide can be deposited to a thickness betweenabout 30 and 40 μm, resulting in a significant spacing between thespiral inductor and additional components (not shown in FIG. 4) that maybe created overlying the surface of layer 34.

[0052] The vias of the invention can be quantified that these viastypically have a diameter between about 3 and 40 μm. An optimumrelationship between the thickness of layer 30 of dielectric and thecreation of the vias can be achieved by having a ratio of via diameterto thickness of layer 30 in the range of about 0.5 and 2.0.

[0053] The creation of the spiral inductor of the invention can furtherbe extended making use of the thick layer of polyimide as is shown incross section in FIG. 5. Shown in FIG. 5 is how the via 36, FIG. 4, hasbeen extended through the layer 34 of polyimide such that the border ofvia 48 is available for further interconnect, and can in this manner beused for instance as a redistribution layer for flip chip interconnects.

[0054] Although the invention has been described and illustrated withreference to specific illustrative embodiments thereof, it is notintended that the invention be limited to those illustrativeembodiments. Those skilled in the art will recognize that variations andmodifications can be made without departing from the spirit of theinvention. It is therefore intended to include within the invention allsuch variations and modifications which fall within the scope of theappended claims and equivalents thereof.

What is claimed is:
 1. A method of creating a spiral inductor,comprising the steps of: providing a substrate, interconnect lineshaving been provided over the surface of said substrate for connectionthereto of inductor terminals; depositing a layer of dielectric over thesurface of said substrate, thereby including the surface of saidinterconnect line; depositing a layer of passivation over the surface ofsaid layer of dielectric; patterning and etching said layer ofdielectric and said layer of passivation, creating first via openingsthrough said layers of dielectric and passivation that are aligned withsaid interconnect lines provided over the surface of said substrate,exposing the surface of said interconnect lines; depositing a firstlayer of metal over the surface of said layer of passivation, includinginside surfaces of said first via openings created through said layersof passivation and dielectric, said first layer of metal being depositedto a thickness between about 6 and 26 μm; patterning and etching saiddeposited first layer of metal, creating metal lines for an inductor,further creating first vias for interconnecting said inductor to saidexposed surfaces of said interconnect lines, said first vias beingconnected to said inductor and forming terminal ports for said inductor;and depositing a thick layer of polyimide over the surface of said layerof passivation, including the surface of said created inductor andinside surfaces of said created first vias.
 2. The method of claim 1wherein said thick layer of polyimide is deposited to a thicknessbetween about 30 and 60 μm.
 3. The method of claim 1 wherein said firstvia has a surface area overlying said layer of passivation of about 7×7μm for application at higher level metal.
 4. The method of claim 1wherein said first via has a surface area overlying said layer ofpassivation larger than about 7×7 μm for application at higher levelmetal.
 5. The method of claim 1 wherein said first layer of metal isdeposited using plating or screen printing techniques.
 6. The method ofclaim 1 wherein said first layer of metal comprises a material selectedfrom the group consisting of gold and copper and platinum.
 7. The methodof claim 1 wherein said first via has a smallest surface area overlyingsaid layer of passivation of about 0.17×0.17 μm, said surface area ofsaid first via overlying said layer of passivation can exceed saidsmallest surface area by a measurable amount.
 8. The method of claim 1with additional step of: creating at least one opening through saidthick layer of polyimide, said at least one opening being aligned withat least one of said first vias created for interconnecting saidinductor to said exposed surfaces of said interconnect lines; depositinga second layer of metal over the surface of said thick layer ofpolyimide, including inside surfaces of said at least one openingcreated through said thick layer of polyimide, said second layer ofmetal being deposited to a thickness between about 6 and 26 μm; andpatterning and etching said second layer of metal, creating at least onesecond via being aligned with at least one of said first vias createdfor interconnecting said inductor to said exposed surfaces of saidinterconnect lines, providing a re-distribution layer on the surface ofsaid thick layer of polyimide for flip chip interconnects.
 9. The methodof claim 8 wherein said second via has a surface area overlying saidlayer of polyimide of about 7×7 μm.
 10. The method of claim 8 whereinsaid second via has a surface area overlying said layer of polyimidelarger than about 7×7 μm.
 11. The method of claim 8 wherein said secondlayer of metal is deposited using plating or screen printing techniques.12. The method of claim 8 wherein said second layer of metal comprises amaterial selected from the group consisting of gold and copper andplatinum.
 13. The method of claim 8 wherein said second via has asmallest surface area overlying said layer of polyimide of about0.17×0.17 μm for application at lower level metal, said surface area ofsaid second via overlying said layer of polyimide can exceed saidsmallest surface area by a measurable amount.
 14. The structure of aspiral inductor, comprising: a substrate, interconnect lines having beenprovided over the surface of said substrate for connection thereto ofinductor terminals; a layer of dielectric deposited over the surface ofsaid substrate, thereby including the surface of said interconnect line;a layer of passivation deposited over the surface of said layer ofdielectric; first via openings created through said layers of dielectricand passivation that are aligned with said interconnect lines providedon the surface of said substrate, exposing the surface of saidinterconnect lines, said first via openings being created large enoughfor the deposition of a layer of metal with a thickness between about 6and 26 μm over inside surfaces of said first vias; a first layer ofmetal deposited over the surface of said layer of passivation, includinginside surface of said first via openings created through said layers ofpassivation and dielectric, said first layer of metal being deposited toa thickness between about 6 and 26 μm; said deposited first layer ofmetal having been patterned and etched, creating metal lines for aninductor, further creating first vias for interconnect said inductor tosaid exposed surfaces of said interconnect lines, said first vias beingconnected to said inductor and forming terminal ports for said inductor;and a thick layer of polyimide deposited over the surface of said layerof passivation, including the surface of said created inductor andinside surfaces of said created first vias.
 15. The structure of claim14, said thick layer of polyimide having a thickness between about 30and 60 μm.
 16. The structure of claim 14, said first via having asurface area overlying said layer of passivation of about 7×7 μm. 17.The structure of claim 14, said first via having a surface areaoverlying said layer of passivation larger than about 7×7 μm.
 18. Thestructure of claim 14, said first layer of metal comprising a materialselected from the group consisting of gold and copper and platinum. 19.The structure of claim 1, said first via having a smallest surface areaoverlying said layer of passivation of about 0.17×0.17 μm forapplication at lower level metal, said surface area of said first viaoverlying said layer of passivation can exceed said smallest surfacearea by a measurable amount.
 20. The structure of claim 14 with theaddition of: at least one opening created through said thick layer ofpolyimide, said at least one opening being aligned with at least one ofsaid first vias created for interconnecting said inductor to saidexposed surfaces of said interconnect lines; a second layer of metaldeposited over the surface of said thick layer of polyimide, includinginside surfaces of said at least one opening created through said thicklayer of polyimide, said second layer of metal being deposited to athickness between about 6 and 26 μm; and at least one second via createdthrough said thick layer of polyimide being aligned with at least one ofsaid first vias created for interconnecting said inductor to saidexposed surfaces of said interconnect lines, providing a re-distributionlayer on the surface of said thick layer of polyimide for flip chipinterconnects.
 21. The structure of claim 20, said second via having asurface area overlying said layer of polyimide of about 7×7 μm.
 22. Thestructure of claim 20, said second via having a surface area overlyingsaid layer of polyimide larger than about 7×7 μm.
 23. The structure ofclaim 20, said second layer of metal being selected from the groupconsisting of gold and copper and platinum.
 24. The structure of claim20, said second via having a smallest surface area overlying said layerof polyimide of about 0.17×0.17 μm for application at lower level metal,said surface area of said second via overlying said layer of polyimidecan exceed said smallest surface area by a measurable amount.